`timescale 1ns/10ps
module mux2 (
    a,b,sel,y
);
input a,b,sel;
output y;

//assign y=sel?a^b:a&b;
reg y; // always 语句块赋值的变量必须为reg型 
always @(a or b or sel) begin
    if(sel==1)begin
        y<=a^b;
    end
    else begin
        y<=a&b;
    end
end
    
endmodule

module  mux2_tb;
reg a,b,sel;
wire y;

mux2 mux2(.a(a),.b(b),.sel(sel),.y(y));

initial begin
    a<=0;b<=0;sel<=0;
    #10
    a<=1;b<=0;sel<=0;
    #10
    a<=1;b<=1;sel<=0;
    #10
    a<=0;b<=0;sel<=1;
    #10
    a<=0;b<=1;sel<=1;
    #10
    a<=1;b<=1;sel<=1;
    #10
    $stop;
end
    
endmodule